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Federal Register / Vol. 86, No. 58 / Monday, March 29, 2021 / Rules and Regulations
e.2. Designed to form an integrated system in a vacuum environment for sequential multiple wafer processing;
Note: 3B001.e does not control automatic robotic wafer handling systems specially designed for parallel wafer processing.
Technical Notes:
1. For the purpose of 3B001.e, semiconductor process tools refers to modular tools that provide physical processes for semiconductor production that
are functionally different, such as deposition, implant or thermal processing.
2. For the purpose of 3B001.e, sequential multiple wafer processing means the capability to process each wafer in different semiconductor process tools, such as by transferring each wafer from one tool to a second tool and on to a third tool with the automatic loading multi-chamber central wafer handling systems.
f. Lithography equipment as follows:
f.1. Align and expose step and repeat direct step on wafer or step and scan
scanner equipment for wafer processing using photo-optical or X-ray methods and having any of the following:
f.1.a. A light source wavelength shorter than 193 nm; or f.1.b. Capable of producing a pattern with a Minimum Resolvable Feature size MRF
of 45 nm or less;
Technical Note: The Minimum Resolvable Feature size MRF is calculated by the following formula:

an exposure light source wavelength in nm x Kfactor MRF=

numerical aperture
Micro contact printing tools Hot embossing tools Nano-imprint lithography tools Step and flash imprint lithography SFIL
tools f.3. Equipment specially designed for mask making having all of the following:
f.3.a. A deflected focused electron beam, ion beam or laser beam; and f.3.b. Having any of the following:
f.3.b.1. A Full-Width Half-Maximum FWHM spot size smaller than 65 nm and an image placement less than 17 nm mean + 3
sigma; or f.3.b.2. Reserved f.3.b.3. A second-layer overlay error of less than 23 nm mean + 3 sigma on the mask;
f.4. Equipment designed for device processing using direct writing methods, having all of the following:
f.4.a. A deflected focused electron beam;
and f.4.b. Having any of the following:
f.4.b.1. A minimum beam size equal to or smaller than 15 nm; or f.4.b.2. An overlay error less than 27 nm mean + 3 sigma;
g. Masks and reticles, designed for integrated circuits controlled by 3A001;
h. Multi-layer masks with a phase shift layer not specified by 3B001.g and designed to be used by lithography equipment having a light source wavelength less than 245 nm;
Note: 3B001.h. does not control multi-layer masks with a phase shift layer designed for the fabrication of memory devices not controlled by 3A001.
N.B.: For masks and reticles, specially designed for optical sensors, see 6B002.
i. Imprint lithography templates designed for integrated circuits by 3A001;

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j. Mask substrate blanks with multilayer reflector structure consisting of molybdenum and silicon, and having all of the following:
j.1. Specially designed for Extreme Ultraviolet EUV lithography; and j.2. Compliant with SEMI Standard P37.
Technical Note: Extreme Ultraviolet EUV refers to electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.

27. In supplement no. 1 to part 774, Category 3, ECCN 3E002 is revised to read as follows:

3E002 Technology according to the General Technology Note other than that controlled in 3E001 for the development or production of a microprocessor microcircuit, microcomputer microcircuit and microcontroller microcircuit core, having an arithmetic logic unit with an access width of 32 bits or more and any of the following features or characteristics see List of Items Controlled.
License Requirements Reason for Control: NS, AT
Controls NS applies to entire entry.
AT applies to entire entry.

Country Chart See Supp. No. 1 to part 738
NS Column 1
AT Column 1

License Requirements Note: See 744.17 of the EAR for additional license requirements for microprocessors having a processing speed of 5 GFLOPS or more and an arithmetic logic unit with an access width of 32 bit or more, including those incorporating information security functionality, and associated software and technology for the production or development of such microprocessors.

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List Based License Exceptions See Part 740
for a Description of All License Exceptions TSR: Yes List of Items Controlled Related Controls: N/A
Related Definitions: N/A
Items:
a. A vector processor unit designed to perform more than two calculations on floating-point vectors one-dimensional arrays of 32-bit or larger numbers simultaneously;
Technical Note: A vector processor unit is a processor element with built-in instructions that perform multiple calculations on floating-point vectors onedimensional arrays of 32-bit or larger numbers simultaneously, having at least one vector arithmetic logic unit and vector registers of at least 32 elements each.
b. Designed to perform more than four 64bit or larger floating-point operation results per cycle; or c. Designed to perform more than eight 16bit fixed-point multiply-accumulate results per cycle e.g., digital manipulation of analog information that has been previously converted into digital form, also known as digital signal processing.
Note 1: 3E002 does not control technology for multimedia extensions.
Note 2: 3E002 does not control technology for microprocessor cores, having all of the following:
a. Using technology at or above 0.130
mm; and b. Incorporating multi-layer structures with five or fewer metal layers.
Note 3: 3E002 includes technology for the development or production of digital signal processors and digital array processors.
Technical Notes:
1. For the purpose of 3E002.a and 3E002.b, floating-point is defined by IEEE754.

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where the K factor = 0.35
f.2 Imprint lithography equipment capable of production features of 45 nm or less;
Note: 3B001.f.2 includes: